Storage capacity of an IC memory is increasing more and more, and accordingly an increased IC chip area and formation of patterns at high density are required. As a result, there is an increased possibility that a reduction of the yield of IC memories caused by a very minute defect occurs. In order to prevent the yield of IC memories from being reduced, there are manufactured IC memories in each of which, for example, a failure memory cell can be electrically replaced by a spare or alternative memory cell (also called a relief line or spare line). The IC memory of this kind is called a memory of redundancy structure in this technical field, and a decision as to whether or not the redundancy-structured memory can be relieved is rendered by referring to failure information (positions of occurrences of failure memory cells, the number of occurrences of failure memory cells, and the like) stored in a failure analysis memory.
FIG. 6 shows a block diagram of a general construction of an example of a conventional memory testing apparatus provided with a failure analysis memory. This memory testing apparatus comprises a pattern generator 11, a logical comparator 12 and a failure analysis memory 13. The pattern generator 11 generates, in response to a reference clock from a timing generator not shown, an address signal, a test pattern signal, a control signal and the like all of which are to be supplied to an IC memory under test (hereinafter also referred to simply as memory under test) MUT as well as generates an expected value signal to be supplied to the logical comparator 12. The test pattern signal is applied to the memory under test MUT, and is written in an address of the memory under test MUT specified by an address signal applied thereto simultaneously with the test pattern signal.
The test pattern signal written in the memory under test NUT is temporarily stored therein and thereafter is read out thereof. The read-out test pattern signal is inputted to the logical comparator 12. An expected value signal from the pattern generator 11 is supplied to the logical comparator 12 where the test pattern signal read out of the memory under test MUT is logically compared with the expected value signal to detect as to whether or not there is an anti-coincidence or mismatch between both signals.
If both signals do not coincide with each other, the logical comparator 12 outputs a failure signal (failure data) having, for example, logic "1" (logic H) to the failure analysis memory 13 to store it therein at an address thereof specified by an address signal supplied through an address bus line 14 from pattern generator 11. Usually, when both the signals coincide with each other, the logical comparator 12 generates a pass signal which is not stored in the failure analysis memory 13.
In such a way, the information on failure memory cells in the memory under test MUT generated during a series of tests is stored in the failure analysis memory 13. After the tests have been completed, a failure analysis for the memory under test MUT is carried out with reference to the failure information stored in the failure analysis memory 13.
For this end, the failure analysis memory 13 has the same operating rate or speed and storage capacity as those of the memory under test MUT, and the same address signal as that applied to the memory under test MUT is applied to the failure analyses memory 13 from the pattern generator 11 via the address bus line 14.
The failure analysis memory 13 is initialized prior to the start of a test. For example, when initialized, the failure analysis memory 13 has data of logic "0s": written in all of the addresses thereof. Every time a failure signal representing that an anti-coincidence is generated from the logical comparator 12 in the test of a memory under test MUT, a failure signal of, for example, logic "1" is written in the same address of the failure analysis memory 13 as that of the memory cell of the memory under test which has generated the anti-coincidence signal, the failure signal of logic "1" representing a failure of that memory cell.
Here, the redundancy-structured memory described above is provided with, as shown in FIG. 6, column (longitudinal row) failure relief lines LX and row (lateral row) failure relief lines LY in addition to a main storage area M. In this example, there is shown a case in which two column failure relief lines LX and two row failure relief lines LY are provided respectively in parallel with one side in the row (lateral row) address direction (left to right direction in the drawing (this direction is defined as X direction)) of the main storage area M of the failure analysis memory 13 and one side in the column (longitudinal row) address direction (up-and-down direction in the drawing (this direction is defined as Y direction)) of the main storage area M thereof.
In case the memory under test MUT is a memory of redundancy structure as shown in FIG. 6, it is needless to say that it is also desired to render a decision as to whether those failure relief lines LX and LY are defective or failures or not. In order to render such decision on the failure relief lines LX and LY, it is necessary to provide in the failure analysis memory 13 a memory area for storing failure positions of memory cells in the failure relief lines LX and LY.
Assuming that the main storage area M of the memory under test MUT shown FIG. 6 has a storage capacity of 1M bits, the storage capacity of the failure analysis memory 13 also has 1M bits which is the same storage capacity as that of the main storage area M of the memory under test MUT, if it is unnecessary to render a decision as to whether or not the failure relief lines LX and LY are defective. However, if it is also necessary to render a decision as to whether or not the failure relief lines LX and LY are defective, the storage capacity of the failure analysis memory 13 must have bits of the sum of 1M bits and additional bits for an additional storage area for storing those failure relief lines LX and LY.
On the other hand, in case only the main storage area M of the memory under test MUT is accessed, the pattern generator 11 suffices to generate a row direction address signal and a column direction address signal the number of bits of each of which has 10 bits (2.sup.10 .times.2.sup.10 =1048576). However, in case the memory under test MUT is accessed on its all addresses including the failure relief lines LX and LY in addition to the main storage area M, the pattern generator 11 must generate the row direction address signal of 11 bits and the column direction address signal of 11 bits (2.sup.11 .times.2.sup.11 =4194304) in which one habit is further added to each of the row direction address signal and the column direction address signal, since it is impossible to access all addresses of the memory under test MUT including the failure relief lines LX and LY and the main storage area M by the row direction address signal of 10 bits and the column direction address signal of 10 bits. That is, address signals capable of accessing a storage area of 4M bits must be generated from the pattern generator 11.
Since the failure analysis memory 13 is generally constructed using one or more commercially available IC memories, it is the case that an IC memory is not commercially available, which has a storage capacity exactly corresponding to the sum of the main storage area M and the storage areas of the failure relief lines LX and LY. For example, although an IC memory having a storage capacity of 1M bits, 2M bits, 4M bits, 8M bits or the like is commercially available, an IC memory having a storage capacity of 1.1M bits, 1.15M bits, 1.2M bits, 1.3M bits or the like is not commercially available. For this reason, heretofore, the failure analysis memory 13 is conventionally constructed, as shown in FIG. 7, using four 1M bit memories MA, MB, MC and MD each of which has the same storage capacity (1M bits) as that of the main storage area M of the memory under test MUT, and failure memory cell positions of the main storage area M of the memory under test MUT are stored in the memory MA and failure memory cell positions of the failure relief lines LX and LY are stored in the remaining three memories MB, MC and MD.
That is, in order to provide in the failure analysis memory 13 a storage area covering the side portions on which the failure relief lines LX and LY on the periphery of the main storage area M of the memory under test MUT are formed respectively, three memories each having the same storage capacity as that of the main storage area M (1M bits) of the memory under test MUT are heretofore used, and therefore, the failure analysis memory 13 has to have its storage capacity of four times the storage capacity of the main storage area M of the memory under test MUT. In addition, in order to access the failure analysis memory 13 of 4M bit capacity, it has been necessary to generate the row direction address signal of 11 bits and the column direction address signal of 11 bits.
As mentioned above, in order to store the very small information of the failure memory cell positions of the failure relief lines LX and LY, the failure analysis memory 13 having its storage capacity of four times that of the main storage area M of the memory under test MUT must be heretofore constructed. Therefore, there is a drawback that the cost needed to manufacture the failure analysis memory 13 becomes high.
In addition, generally, there are many cases in the memory testing apparatus of this type that a plurality of memories under test are measured at the same time. In case there is a limitation on the total storage capacity of the failure analysis memory 13, if the storage capacity of one failure analysis memory 13 is large, the number of failure analysis memories which can be provided in one memory testing apparatus is reduced. Since the number of the memories under test to be measured at the same time in one test is equal to the number of the failure analysis memories, there is also a disadvantage that the number of memories under test to be measured at the same time is decreased, and hence the efficiency of test becomes deteriorated (throughput is lowered).